Clocks and Power Control
5-8
MPC823e REFERENCE MANUAL
MOTOROLA
CLOCKS AND POWER
5
CONTROL
SPLSS—System PLL Lock Status Sticky
This bit is not affected by hard reset. An out-of-lock indication sets the SPLSS bit and it
remains set until the software clears it. At power-on reset, the state of the SPLSS bit is zero.
Write a 1 to clear this bit (writing a zero has no effect). Notice that a loss-of lock caused by
a change in the MF field or the processor entering deep-sleep mode or power-down mode
does not affect the SPLSS bit. Only a loss-of-lock not caused by the following conditions will
set this bit.
0 = SPLL remains locked.
1 = SPLL has gone out of lock at least once since the bit was cleared or at the last
power-on reset.
TEXPS—Timer Expired Status
This internal status bit is set when the periodic timer expires, the real-time clock alarm sets,
the timebase clock alarm sets, the decrementer interrupt occurs, or the system resets. The
TEXP pin reflects the value of the TEXPS bit, so you have to read the pin to find out the
status of the bit. You can clear this bit by writing a 1 (writing a zero has no effect). When
TEXPS is set, the TEXP external signal is asserted and, when it is reset, TEXP is negated.
0 = TEXP is negated.
1 = TEXP is asserted.
Bits 18, 20, and 27–31—Reserved
These bits are reserved and must be set to 0.
TMIST—Timers Interrupt Status
This bit is cleared at reset and is set when a real-time clock, periodic interrupt timer,
timebase, or decrementer interrupt occurs. You can clear this bit by writing a 1 (writing a
zero has no effect). When the TMIST bit is set, the system clock switches to high frequency,
as defined by the DFNH field. The system clock frequency stays high if the CSRC bit is set
and there is no reason to switch to normal low mode.
0 = No timer interrupt is detected.
1 = A timer interrupt is detected.
CSRC—Clock Source
This bit specifies whether the DFNH or DFNL field generates the general system clock. This
bit is cleared by a hard reset.
0 = The general system clock is generated by the DFNH field.
1 = The general system clock is generated by the DFNL field.
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