Development Capabilities and Interface
MOTOROLA MPC823e REFERENCE MANUAL 20-33
DEVELOPMENT
20
CAPABILITIES & INTERFACE
Figure 20-9. Asynchronous Clocked Serial Communications Timing Diagram
DSCK
DSDI MODE CNTRL DI<0>
S<0> S<1> DO<0>
START
READY
DSDO
DEBUG PORT DRIVES THE “READY” BIT ONTO DSDO WHEN READY FOR A NEW TRANSMISSION.
NOTE: DSCK AND DSDI TRANSITIONS ARE NOT REQUIRED TO BE SYNCHRONOUS WITH CLKOUT.
DI<N-2>
DI<N-1> DI<N>
DO<N-2> DO<N-1> DO<N>
DEBUG PORT DETECTS THE “START” BIT ON DSDI AND FOLLOWS THE “READY” BIT
WITH TWO STATUS BITS AND 7 OR 32 OUTPUT DATA BITS.
DEVELOPMENT TOOL DRIVES THE “START” BIT ON DSDI (AFTER DETECTING THE “READY” BIT ON DSDO
WHEN IN DEBUG MODE). THE “START BIT IS IMMEDIATELY FOLLOWED BY A MODE BIT AND A CONTROL
BIT AND THEN 7 OR 32 INPUT DATA BITS.
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