Motorola MPC823e - Page 1142

IEEE 1149.1 Test Access Port
MOTOROLA MPC823e REFERENCE MANUAL 21-21
IEEE 1149.1 TEST
21
ACCESS PORT
21.4 MPC823e RESTRICTIONS
The control afforded by the output enable signals using the boundary scan register and the
extest instruction requires a compatible circuit board test environment to avoid
device-destructive configurations. You must avoid situations in which the MPC823e output
drivers are enabled into actively driven networks. The MPC823e features a low-power stop
mode. The interaction of the scan chain interface with low-power stop mode is as follows:
1. The TAP controller must be in the test-logic-reset state to either enter or remain in the
low-power stop mode. Leaving the TAP controller in the test-logic-reset state negates
its ability to achieve low power, but does not otherwise affect device functionality.
2. The TCK input is not disabled in low-power stop mode. To consume minimal power,
the TCK input must be externally connected to V
CC
or ground while in low-power or
normal mode (nonscan chain).
3. The TMS, TDI, and TRST pins include on-chip pull-up resistors. In low-power stop
mode, the TMS and TDI pins must remain either unconnected or connected to V
CC
to
achieve minimal power consumption. For proper reset of the scan chain test logic, the
best approach is to pull active TRST
at power-on reset. The easiest way to do this and
reset the scan chain logic is to connect TRST
to PORESET through a diode (cathode
to PORESET). In power-down mode, you must ensure that the xRESET line is low
during power-down so that you can conserve power. If the TAP controller is not used,
you must ground the TRST signal. If, for some reason, the HRESET
signal that you
connected to TRST
is high during power-down, the KAPWR supply will propagate
through the TRST
pin to undesired internal circuits and will increase power
consumption.
]
Note: We recommend that you connect TRST to ground (if you don't use JTAG) or to
PORESET
through a diode. The problem with the connection to HRESET is that
if at power up the JTAG logic blocks the PORESET
signal from propagating into
the chip (since the logic is not initialized yet), this will prevent HRESET
from
asserting, which leaves the JTAG logic (and the whole device) uninitialized.