Motorola MPC823e - Page 1165

MPC823e Instruction Set—add
MOTOROLA MPC823e REFERENCE MANUAL B-7
INSTRUCTION SET
B
add
Assembler Syntax add r D, r A, r B (OE = 0 Rc = 0)
add. r D, r A, r B (OE = 0 Rc = 1)
addo r D, r A, r B (OE = 1 Rc = 0)
addo. r D, r A, r B (OE = 1 Rc = 1)
Operation rD " (rA) + (rB)
Description The sum ( r A) + ( r B) is placed into r D. The add instruction is
preferred for addition because it sets few status bits.
Other registers altered:
❏ Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
The CR0 field may not reflect the “true” (infinitely precise)
result if overflow occurs (see XER below).
❏ XER:
Affected: SO, OV (if OE = 1)
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD 31 D A
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD B OE 266 RC
POWERPC ARCHITECTURE
LEVEL
SUPERVISOR
LEVEL
OPTIONAL FORM
UISA XO