Motorola MPC823e - Page 13

TABLE OF CONTENTS (Continued)
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Number Title Number
MOTOROLA MPC823e REFERENCE MANUAL xi
15.3.1.2 Option Registers .........................................................15-11
15.3.1.3 Memory Status Register .............................................15-15
15.3.1.4 Memory Command Register .......................................15-17
15.3.1.5 Machine A Mode Register ..........................................15-19
15.3.1.6 Machine B Mode Register ..........................................15-22
15.3.1.7 Memory Data Register ................................................15-26
15.3.1.8 Memory Address Register ..........................................15-26
15.3.1.9 Memory Periodic Timer Prescaler Register ................15-27
15.4 The General-Purpose Chip-Select Machine .....................................15-27
15.4.1 Configuration ..........................................................................15-27
15.4.1.1 Programmable Wait State Configuration ....................15-34
15.4.1.2 Extended Hold Time on Read Accesses ....................15-34
15.4.1.3 Boot Chip-Select Operation ........................................15-37
15.4.1.4 SRAM Interface ..........................................................15-38
15.4.1.5 External Asynchronous Master support ......................15-38
15.5 User-Programmable Machines .........................................................15-41
15.5.1 Requests ................................................................................15-42
15.5.1.1 Internal/External Memory Access Requests ...............15-43
15.5.1.2 Memory Periodic Timer Requests ..............................15-43
15.5.1.3 Software Requests .....................................................15-44
15.5.1.4 Exception Requests ....................................................15-44
15.5.2 Programming the User-Programmable Machine ....................15-44
15.5.3 Clock Timing ...........................................................................15-45
15.5.4 The RAM Array .......................................................................15-49
15.5.4.1 The RAM Word ...........................................................15-50
15.5.4.1.1 RAM Word Format .........................................15-50
15.5.4.2 RAM Word Operation .................................................15-55
15.5.4.2.1 Start Addresses ..............................................15-55
15.5.4.2.2 Chip-Select Signals ........................................15-56
15.5.4.2.3 Byte-Select Signals ........................................15-57
15.5.4.2.4 General-Purpose Signals ...............................15-59
15.5.4.2.5 Loop Control ...................................................15-60
15.5.4.2.6 Exception Handling ........................................15-60
15.5.4.2.7 Address Multiplexing ......................................15-61
15.5.4.2.8 Transfer Acknowledge and Data Sample
Control ............................................................15-65
15.5.4.2.9 Disable Timer Mechanism ..............................15-65
15.5.4.2.10 Last Word .......................................................15-65
15.5.5 The Wait Mechanism ..............................................................15-66
15.5.5.1 Internal and External Synchronous Master .................15-66
15.5.5.2 External Asynchronous Master ...................................15-67
15.5.5.3 Handling Variable Access Time and Slow Devices ....15-68