Motorola MPC823e - Page 212

Data Cache
10-8 MPC823e REFERENCE MANUAL MOTOROLA
DATA CACHE
10
The DC_ADR must be configured into the following fields before the internal parts of the
data cache are read from the DC_DAT register.
Bits 0–17 and 28–31—Reserved
These bits are reserved and must be set to 0.
RT—Register or Tag Selection
0 = Select tag operation.
1 = Select register operation.
WAY—Way Selection
0 = Select Way 0 of the cache array.
1 = Select Way 1 of the cache array.
SET—Set Selection
This field is used to select the index of the cache array. When RT is set to 1, it specifies the
register to be read. The following registers and their encoding are supported:
•0 × 00—Copyback data register 0
•0 × 01—Copyback data register 1
•0 × 02—Copyback data register 2
•0 × 03—Copyback data register 3
•0 × 04—Copyback address register
When reading from the DC_DAT register, the 20 bits of the tag (and related information) that
is selected by the DC_ADR are placed in the targeted general-purpose register. The
DC_ADR (CACHE READ COMMAND FORMAT)
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD RESERVED
RESET —
R/W R/W
SPR 569
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD RESERVED RT WAY SET RESERVED
RESET ——— — —
R/W R/W R/W R/W R/W R/W
SPR 569
NOTE: — = Undefined.