LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
MOTOROLA
MPC823e REFERENCE MANUAL
xxxiii
11-2. Two Level Translation Table When MD_CTR(TWAM) = 1 ............................11-6
11-3. Two Level Translation Table When MD_CTR(TWAM) = 0 ............................11-7
11-4. Organization of the Memory Management Unit Registers ...........................11-15
Section 12
System Interface Unit
12-1. System Configuration and Protection Logic ...................................................12-4
12-2. MPC823e Interrupt Structure .........................................................................12-5
12-3. Interrupt Table Handling Example ................................................................12-11
12-4. Real-Time Clock Block Diagram ..................................................................12-17
12-5. Periodic Interrupt Timer Block Diagram .......................................................12-22
12-6. Software Watchdog Timer Service State Diagram .......................................12-26
12-7. Software Watchdog Timer Block Diagram ...................................................12-27
Section 13
External Bus Interface
13-1. Input Sample Window ....................................................................................13-2
13-2. MPC823e Bus Signals ...................................................................................13-3
13-3. Basic Flow Diagram of a Single Beat Read Cycle .........................................13-9
13-4. Single Beat Read Cycle–Basic Timing–Zero Wait States ............................13-10
13-5. Single Beat Read Cycle–Basic Timing–One Wait State ..............................13-11
13-6. Basic Flow Diagram of a Single Beat Write Cycle .......................................13-12
13-7. Single Beat Write Cycle–Basic Timing–Zero Wait States ............................13-13
13-8. Single Beat Write Cycle of One Wait State ..................................................13-14
13-9. Single Beat, 32-Bit Data, Write Cycle From a 16-Bit Port Size ....................13-15
13-10. Basic Flow Diagram Of A Burst Read Cycle ................................................13-17
13-11. Burst-Read Cycle–32-Bit Port Size–Zero Wait State ...................................13-18
13-12. Burst-Read Cycle–32-Bit Port Size–One Wait State ....................................13-19
13-13. Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats ................13-20
13-14. Basic Flow Diagram of a Burst Write Cycle .................................................13-21
13-15. Burst-Read Cycle–16-Bit Port Size–One Wait State Between Beats ..........13-22
13-16. Burst-Write Cycle–32-Bit Port Size–Zero Wait States .................................13-23
13-17. Burst-Inhibit Cycle–32-Bit Port Size .............................................................13-24
13-18. Internal Operand Representation .................................................................13-25
13-19. Interface To Different Port Size Devices ......................................................13-26
13-20. Bus Arbitration Flowchart .............................................................................13-28
13-21. Basic Bus Busy Connection .........................................................................13-29
13-22. Bus Arbitration Timing Diagram ...................................................................13-30
13-23. Internal Bus Arbitration State Machine .........................................................13-31
13-24. Termination Signals Protocol Basic Connection ..........................................13-37
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