LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
xxxiv
MPC823e REFERENCE MANUAL
MOTOROLA
13-25. Termination Signals Protocol Timing Diagram .............................................13-37
13-26. Reservation On Local Bus ...........................................................................13-39
13-27. Reservation On Multilevel Bus Hierarchy ....................................................13-41
13-28. RETRY
Transfer Timing–Internal Arbiter .....................................................13-43
13-29. RETRY
Transfer Timing–External Arbiter ....................................................13-44
13-30. Retry On Burst Cycle ...................................................................................13-45
Section 14
Endian Modes
14-1. General MPC823e System Diagram ..............................................................14-2
Section 15
Memory Controller
15-1. Memory Controller Block Diagram (Single UPM) ...........................................15-3
15-2. Memory Controller Machine Selection ...........................................................15-4
15-3. Simple System Configuration .........................................................................15-5
15-4. Basic Memory Controller Operation ...............................................................15-7
15-5. GPCM Memory Device Interface .................................................................15-29
15-6. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, and
TRLX = 0) ....................................................................................................15-30
15-7. GPCM Peripheral Device Interface ..............................................................15-31
15-8. GPCM Peripheral Device Basic Timing (ACS = 10 or 11 and
TRLX = 0) ....................................................................................................15-31
15-9. MPC823e GPCM–Relaxed Timing–Read Access (ACS = 10 or 11,
SCY = 1, and TRLX = 1) ..............................................................................15-32
15-10. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 10 or 11,
SCY = 0, CSNT = 0, and TRLX = 1) ............................................................15-33
15-11. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 10 or 11,
SCY = 0, CSNT = 1, and TRLX = 1) ............................................................15-33
15-12. MPC823e GPCM–Relaxed Timing–Write Access (ACS = 00, SCY = 0,
CSNT = 1, and TRLX = 1) ...........................................................................15-34
15-13. GPCM Read Followed By Write (EHTR = 0) ...............................................15-35
15-14. GPCM Write Followed By Read (EHTR = 1) ...............................................15-35
15-15. GPCM Read Followed By Read From Different Banks (EHTR = 1) ............15-36
15-16. GPCM Read Followed By Read From Same Bank (EHTR = 1) ..................15-36
15-17. GPCM to SRAM Configuration ....................................................................15-38
15-18. Asynchronous External Master Configuration For GPCM-Handled
Memory Devices ..........................................................................................15-38
15-19. Asynchronous External Master, GPCM-Handled Memory Access
Timing (TRLX = 0) .......................................................................................15-39
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