Memory Controller
15-10
MPC823e REFERENCE MANUAL
MOTOROLA
MEMORY CONTROLLER
15
BA—Base Address
This field, the upper 17 bits of each base address register, and the AT field are compared
to the address on the address bus to determine if a memory bank controlled by the memory
controller is being accessed by an internal bus master. These bits are used in conjunction
with the AM field of the option register.
AT—Address Type
This field can be used to limit accesses to the memory bank to a certain address space type.
These bits are used in conjunction with the ATM field of the option register.
PS—Port Size
This field specifies the port size of the memory region. After system reset, the value of this
bit in BR0 depends on the BPS field value in the hard reset configuration word, which is
described in
Section 4.3.1.1 Hard Reset Configuration Word.
00 = 32-bit port size.
01 = 8-bit port size.
10 = 16-bit port size.
11 = Reserved.
PARE—Parity Enable
This bit is used to enable parity checking on this bank.
0 = Parity checking is disabled.
1 = Parity checking is enabled.
WP—Write-Protect
This bit may restrict write accesses within the address range of a base register. If you try to
write to the range of addresses specified in a base address register that has this bit set, the
bus monitor logic asserts the TEA
signal which then terminates the cycle.
0 = Both read and write accesses are allowed.
1 = Only read accesses are allowed. The CSx
and TA signals are not asserted by the
memory controller on write cycles to this memory bank. The WPER bit is set in the
MSTAT register if you try to write to this memory bank.
MS—Machine Select
This field specifies the machine that is selected for memory operations handling.
00 = GPCM.
01 = Reserved.
10 = UPMA.
11 = UPMB.
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