Memory Controller
15-14 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY CONTROLLER
15
If you want to use an external TA response (SETA bit = 1), then these bits are not used.
0000 = 0 clock cycle wait state.
0001 = 1 clock cycle wait state.
0010 = 2 clock cycle wait states.
0011 = 3 clock cycle wait states.
0100 = 4 clock cycle wait states.
0101 = 5 clock cycle wait states.
0110 = 6 clock cycle wait states.
0111 = 7 clock cycle wait states.
1000 = 8 clock cycle wait states.
1001 = 9 clock cycle wait states.
1010 = 10 clock cycle wait states.
1011 = 11 clock cycle wait states.
1100 = 12 clock cycle wait states.
1101 = 13 clock cycle wait states.
1110 = 14 clock cycle wait states.
1111 = 15 clock cycle wait states.
SETA—Select External Transfer Acknowledge (GPCM only)
This bit indicates when the TA
signal is externally generated once the GPCM is selected to
handle the memory access that was initiated to this memory region. Regardless of other
setup parameters for the GPCM, if SETA = 1, then all control signals of the memory
controller are negated after the externally generated TA
signal is recognized.
0 = Internal or external transfer acknowledge can acknowledge this memory access,
whichever comes first.
1 = Transfer acknowledge must be provided by external logic.
TRLX—Timing Relaxed (GPCM only)
When this bit is set, it extends the timing of the signals controlling the memory devices once
the GPCM is selected to handle the memory access that was initiated to this memory region.
Refer to Table 15-2 (page 15-28) for more information.
0 = Timing is defined by the GPCM.
1 = Relaxed timing is defined by the GPCM.
Note: Regardless of other GPCM setup parameters, if the SETA bit equals one, then
all memory controller signals are negated after the externally generated TA
signal is recognized.
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