Motorola MPC823e - Page 39

LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
MOTOROLA MPC823e REFERENCE MANUAL xxxvii
16-41. Single-Address, Peripheral Read, Synchronous TA
..................................16-105
16-42. IDMA Single-Address Burst Read or Write ................................................16-111
16-43. Serial Interface Block Diagram ...................................................................16-113
16-44. Various Configurations With the TDM Channel .........................................16-116
16-45. Enabling Connections Through the Serial Interface ...................................16-117
16-46. Configuring the TDM with Static Frames ...................................................16-118
16-47. Configuring the TDM with Dynamic Frames ..............................................16-119
16-48. Configuring two TDMs with Static Frames .................................................16-120
16-49. Configuring Two TDMs with Dynamic Frames ...........................................16-121
16-50. Using the SWTR Bit ...................................................................................16-122
16-51. Serial Interface RAM Dynamic Changes ....................................................16-127
16-52. Example of One Clock Delay from Sync to Data (RFSDx = 01) ................16-132
16-53. Example of No Delay from Sync to Data (RFSDx = 00) ............................16-132
16-54. Example of Clock Edge (CE) Effect When DSCx = 0 ................................16-133
16-55. Example of Clock Edge (CE) Effect When DSCx = 1 ................................16-133
16-56. Example of Frame Transmission Reception When RFSDx or TFSDx = 0
and CD = 1 .................................................................................................16-134
16-57. Example of CEx = 0 and FEx Interaction, XFSD = 0 .................................16-135
16-58. IDL Bus Application Example .....................................................................16-144
16-59. IDL Terminal Adaptor .................................................................................16-146
16-60. IDL Bus Signals ..........................................................................................16-147
16-61. GCI Bus Signals .........................................................................................16-150
16-62. Bank of Clocks ...........................................................................................16-155
16-63. Baud Rate Generator Block Diagram .........................................................16-157
16-64. Serial Communication Controller Block Diagram .......................................16-164
16-65. SCCx Memory Structure ............................................................................16-180
16-66. RTSx
Output Delays Asserted for Synchronous Protocols ........................16-189
16-67. CTSx
Output Delays Asserted for Synchronous Protocols ........................16-190
16-68. CTSx
Lost in Synchronous Protocols .........................................................16-191
16-69. Using CDx
to Control Synchronous Protocol Reception ............................16-192
16-70. DPLL Receiver Block Diagram ...................................................................16-195
16-71. DPLL Transmitter Block Diagram ...............................................................16-194
16-72. DPLL Encoding Examples .........................................................................16-196
16-73. Serial IrDA Link ..........................................................................................16-198
16-74. UART Character Format ............................................................................16-201
16-75. Two UART Multidrop Mode Configuration Examples .................................16-209
16-76. SCC2 UART Receive Buffer Descriptor Example ......................................16-221
16-77. SCCx UART Interrupt Event Example .......................................................16-227
16-78. SCCx HDLC Framing Structure .................................................................16-234
16-79. HDLC Address Recognition Example ........................................................16-238
16-80. SCC2 HDLC Receive Buffer Descriptor Example ......................................16-245
16-81. HDLC Interrupt Event Example ..................................................................16-251