Motorola MPC823e - Page 38

LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
xxxvi MPC823e REFERENCE MANUAL MOTOROLA
Section 16
Communication Processor Module
16-1. CPM Block Diagram .......................................................................................16-3
16-2. Example of a PDA Application .......................................................................16-4
16-3. RISC Microcontroller Block Diagram .............................................................16-5
16-4. Dual-Port RAM Block Diagram ....................................................................16-13
16-5. Dual-Port RAM Memory Map .......................................................................16-14
16-6. RISC Timer Table RAM Usage ....................................................................16-18
16-7. DSP Functionality Implementation ...............................................................16-26
16-8. DSP Function Descriptor Operation .............................................................16-28
16-9. Circular Buffer ..............................................................................................16-29
16-10. DSP Implementation Example .....................................................................16-35
16-11. Core and CPM Implementation ....................................................................16-37
16-12. FIR1 Implementation Example .....................................................................16-39
16-13. FIR1 Coefficients and Sample Data Buffers ................................................16-39
16-14. FIR2 Implementation Example .....................................................................16-42
16-15. FIR2 Coefficients and Sample Data Buffers ................................................16-43
16-16. FIR2 Implementation Example .....................................................................16-46
16-17. FIR3 Coefficients and Sample Data Buffers ................................................16-47
16-18. FIR5 Implementation Example .....................................................................16-50
16-19. FIR5 Coefficients and Sample Data Buffers ................................................16-51
16-20. FIR6 Implementation Example .....................................................................16-54
16-21. FIR6 Coefficients and Sample Data Buffers ................................................16-55
16-22. IIR Implementation Example ........................................................................16-57
16-23. IIR Coefficients and Sample Data Buffers ...................................................16-58
16-24. MOD Implementation Example ....................................................................16-60
16-25. MOD Table and Sample Data Buffers .........................................................16-60
16-26. DEMOD Implementation Example ...............................................................16-62
16-27. DEMOD Modulation Table and Sample Data Buffers ..................................16-63
16-28. LMS1 Implementation Example ...................................................................16-65
16-29. LMS1 Coefficients and Sample Data Buffers ...............................................16-65
16-30. LMS2 Implementation Example ...................................................................16-67
16-31. LMS2 Coefficients and Sample Data Buffers ...............................................16-68
16-32. WADD Implementation Example .................................................................16-70
16-33. WADD Modulation Table and Sample Data Buffers ....................................16-71
16-34. Timer Block Diagram ...................................................................................16-74
16-35. Timer Cascaded Mode Block Diagram ........................................................16-76
16-36. SDMA Data Paths ........................................................................................16-83
16-37. SDMA Bus Arbitration ..................................................................................16-84
16-38. IDMA Buffer Descriptor Ring ........................................................................16-91
16-39. Single-Address, Peripheral Write, Asynchronous TA
................................16-103
16-40. Single-Address, Peripheral Write, Synchronous TA
..................................16-104