Memory Controller
MOTOROLA
MPC823e REFERENCE MANUAL
15-49
MEMORY CONTROLLER
15
MEMORY CONTROLLER
15
15.5.4.1 THE RAM WORD.
The RAM word is a 32-bit wide micro-instruction that is stored
in one of 64 locations in the RAM array.
15.5.4.1.1 RAM Word Format.
The RAM word format selects and specifies the timing of all
external signals controlled by the user-programmable machine.
CST4—Chip-Select Timing 4
This bit defines the state of the CSx
signal during clock phase 1.
0 = The CSx
signal is asserted at the trailing edge of GCLK2.
1 = The CSx
signal is negated at the trailing edge of GCLK2.
CST1—Chip-Select Timing 1
This bit defines the state of the CSx signal during clock phase 2.
0 = The CSx
signal is asserted at the rising edge of GCLK1.
1 = The CSx
signal is negated at the rising edge of GCLK1.
CST2—Chip-Select Timing 2
This bit defines the state of the CSx
signal during clock phase 3.
0 = The CSx
signal is asserted at the rising edge of GCLK2.
1 = The CSx
signal is negated at the rising edge of GCLK2.
RAM WORD
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
CST4 CST1 CST2 CST3 BST4 BST1 BST2 BST3 G0L G0H G1T4 G1T3 G2T4 G2T3
RESET
———————— — — ————
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(MCR
MAD
) INDIRECT ADDRESSING OF 1 OF 64 ENTRIES
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
G3T4 G3T3
G4T4/
DLT3
G4T3/
WAEN
G5T4 G5T3 RESERVED LOOP EXEN AMX NA UTA TODT LAST
RESET
—————— — —— — ————
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
*
NOTE:
*
All 32 bits of the RAM word are addressed as shown in the address row above.
— = Undefined.
Note:
The state of the selected CSx
signal depends on the value of each CSTx bit and
the corresponding bank.
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