Motorola MPC823e - Page 408

Memory Controller
15-50 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY CONTROLLER
15
CST3—Chip-Select Timing 3
This bit defines the state of the CSx
signal during clock phase 4.
0 = The CSx
signal is asserted at the trailing edge of GCLK1.
1 = The CSx
signal is negated at the trailing edge of GCLK1.
BST4—Byte-Select Timing 4
This bit defines the state of the BSx
signal during clock phase 1.
0 = The BSx
signal is asserted at the trailing edge of GCLK2.
1 = The BSx
signal is negated at the trailing edge of GCLK2.
BST1—Byte-Select Timing 1
This bit defines the state of the BSx
signal during clock phase 2.
0 = The BSx
signal is asserted at the rising edge of GCLK1.
1 = The BSx
signal is negated at the rising edge of GCLK1.
BST2—Byte-Select Timing 2
This bit defines the state of the BSx
signal during clock phase 3.
0 = The BSx
signal is asserted at the rising edge of GCLK2.
1 = The BSx
signal is negated at the rising edge of GCLK2
BST3—Byte-Select Timing 3
This bit defines the state of the BSx
signal during clock phase 4.
0 = The BSx
signal is asserted at the trailing edge of GCLK1.
1 = The BSx
signal is negated at the trailing edge of GCLK1.
G0L—General-Purpose Line 0 Lower
This field defines the state of the GPL0
signal during clock phases 1 through 3.
10 = The GPL0
signal is asserted at the trailing edge of GCLK2.
11 = The GPL0
signal is negated at the trailing edge of GCLK2.
00 = The GPL0
signal is driven at the trailing edge of GCLK2 as defined in the G0CLx
field of the MxMR.
Note: The state of each BSx
signal depends on the value of each BSTx bit and three
other parameter values—the PS field in the selected base register and the TSIZx
and A[30:31] signals in the currently accessed cycle.