Motorola MPC823e - Page 410

Memory Controller
15-52 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY CONTROLLER
15
G4T4/DLT3—General-Purpose Line 4 Timing 4/Delay Time 3
This bit performs two functions depending on the value of the GPLx4DIS bit in the machine
mode register. If the MxMR defines the UPWAITx/GPL_x4
pin as an output (GPL_x4), then
this bit functions as G4T4. If it is defined as an input (UPWAITx), then this bit functions as
DLT3.
If you have configured GPLx4DIS = 0 in the MxMR, then you have selected G4T4:
0 = The value of the GPL4
signal at the trailing edge of GCLK2 will be 0.
1 = The value of the GPL4
signal at the trailing edge of GCLK2 will be 1.
If you have configured GPLx4DIS = 1 in the MxMR, then you have selected UPWAITx
and DLT3 is the controlling function:
0 = The data bus must be sampled at the rising edge of GCLK2 for all reads.
1 = The data bus must be sampled at the falling edge of GCLK2 for all reads.
G4T3/WAEN—General-Purpose Line 4 Timing 3/Wait Enable
This bit performs two functions depending on the value of the GPLx4DIS bit in the machine
mode register. If the MxMR defines the UPWAITx/GPL_x4
pin as an output (GPL_x4), then
this bit functions as G4T3. If it is defined as an input (UPWAITx), this bit functions as WAEN.
If you have configured GPLx4DIS = 0 in the MxMR, then you have selected G4T3:
0 = The value of the GPL4
signal at the trailing edge of GCLK1 will be 0.
1 = The value of the GPL4
signal at the trailing edge of GCLK1 will be 1.
If you have configured GPLx4DIS = 1 in the MxMR, then you have selected UPWAITx
and WAEN is the controlling function:
0 = The UPWAITx function is disabled.
1 = A “freeze” in the logical value of the UPM-controlled external signals will occur
when the UPWAITx pin is asserted. The UPWAITx signal is sampled on the trailing
edge of GCLK2. See Figure 15-33 for more information.
G5T4—General-Purpose Line 5 Timing 4
This bit defines the state of the GPL5
signal during clock phases 1 through 3.
0 = The value of the GPL5
signal at the trailing edge of GCLK2 will be 0.
1 = The value of the GPL5
signal at the trailing edge of GCLK2 will be 1.
G5T3—General-Purpose Line 5 Timing 3
This bit defines the state of the GPL5
signal during clock phase 4.
0 = The value of the GPL5
signal at the trailing edge of GCLK1 will be 0.
1 = The value of the GPL5
signal at the trailing edge of GCLK1 will be 1.
Bits 22 and 23—Reserved
These bits are reserved and must be set to 0.