Motorola MPC823e - Page 422

Memory Controller
15-64 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY CONTROLLER
15
15.5.4.2.8 Transfer Acknowledge and Data Sample Control. During a memory access,
the UTA bit of the RAM word controls the state of the TA
signal sampled by the bus master.
The TA
signal is driven on the rising edge of GCLK2. When a read access is handled by the
UPM and the UTA bit is 0, the value of the DLT3 bit in the same RAM word indicates when
the data input is sampled by the bus master, assuming that the GPLx4DIS bit is set in the
MxMR. Figure 15-32 illustrates the data sampling that is controlled by the UPM.
15.5.4.2.9 Disable Timer Mechanism. The disable timer associated with each UPM
allows you to guarantee a minimum time between two successive accesses to the same
memory bank. This feature is critical when DRAM requires a RAS
precharge time. The
TODT bit in the RAM word turns the timer on to prevent another UPM access to the same
bank until the timer expires.
The disable timer does not affect memory accesses to different banks. If the timing specified
by the UPM RAM word is less than the disable timer period, the access to the next bank will
conflict with the current bank access. To avoid conflicts between different banks using the
same UPM, the number of words in the RAM array must be equal to or greater than the
period defined in the DSx field of the MxMR.
15.5.4.2.10 Last Word. When the LAST bit is read in the RAM word, the highest priority
pending request (if any) is serviced immediately in the external memory transactions. If the
disable timer is activated, the bus will be idle for a number of clock cycles, as specified in
the DSx field of the MxMR.
Figure 15-32. UPM Read Access Data Sampling
TO INTERNAL
DATA BUS
GCLK2
DATA BUS
MULTIPLEXER
LATCH
LATCH
DLT3 AND GPLx4DIS