Motorola MPC823e - Page 431

Memory Controller
MOTOROLA MPC823e REFERENCE MANUAL 15-73
MEMORY CONTROLLER
15
MEMORY CONTROLLER
15
Figure 15-38. Synchronous External Master–Burst Read Access To Page Mode DRAM
cst4 (Bit 0) 000000000
cst1 (Bit 1) 000000000
cst2 (Bit 2) 000000001
cst3 (Bit 3) 000000001
bst4 (Bit 4) 110101010
bst1 (Bit 5) 100000000
bst2 (Bit 6) 101010101
bst3 (Bit 7) 101010101
g0l0 (Bit 8)
≈
g5t4 (Bit 20) 011111111
g5t3 (Bit 21) 000000000
- (Bit 22)
- (Bit 23)
loop (Bit 24) 000000000
exen (Bit 25) 001010100
amx0 (Bit 26) 000000000
amx1 (Bit 27) 000000000
na (Bit 28) 001010100
uta (Bit 29) 101010101
todt (Bit 30) 000000001
last (Bit 31) 000000001
RBS RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8
CLKOUT
GCLK1
A[6:31]
TS
RD/ WR
D[0:31]
TA
CS1
BS [0:3]
( CAS [0:3])
(
RAS )
BURST
A[28:29]
GPL_A5
10
11
00 01