Motorola MPC823e - Page 437

Memory Controller
MOTOROLA MPC823e REFERENCE MANUAL 15-79
MEMORY CONTROLLER
15
MEMORY CONTROLLER
15
Figure 15-43. Single Beat Write Access To Page Mode DRAM
cst4 Bit 0 0 0 0
cst1 Bit 1 0 0 0
cst2 Bit 2 0 0 1
cst3 Bit 3 0 0 1
bst4 Bit 4 1 1 0
bst1 Bit 5 1 0 0
bst2 Bit 6 1 0 1
bst3 Bit 7 1 0 1
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t4 Bit 12
g1t3 Bit 13
g2t4 Bit 14
g2t3 Bit 15
g3t4 Bit 16
g3t3 Bit 17
g4t4 Bit 18
g4t3 Bit 19
g5t4 Bit 20
g5t3 Bit 21
- Bit 22
- Bit 23
loop Bit 24 0 0 0
exen Bit 25 0 0 0
amx0 Bit 26 0 0 0
amx1 Bit 27 0 0 0
na Bit 28 0 0 0
uta Bit 29 1 0 1
todt Bit 30 0 0 1
last Bit 31 0 0 1
WSS WSS+1 WSS+2
CLKOUT/GCLK2
GCLK1
A[6:31]
TS
RD/ WR
D[0:31]
TA
CS1
BS_A [0:3]
( CAS [0:3])
(
RAS )
ROW COLUMN