Communication Processor Module
16-26 MPC823e REFERENCE MANUAL MOTOROLA
DSP
COMMUNICATION
16
PROCESSOR MODULE
16.3 DIGITAL SIGNAL PROCESSING
Many embedded control applications require DSP-style algorithm implementations, such as
finite impulse response (FIR) filters with or without adaptive equalization, data compression,
and scrambling. These are written in software on the MPC823e and do not require your
system to have a separate DSP processor, which would cost you more and consume more
power. The communication processor module provides the additional power you need for
those applications.
The RISC microcontroller’s instruction set supports high-performance multiply and
accumulate (MAC) operation as well as special addressing modes that are essential to
efficient DSP algorithm implementation. The RISC microcontroller runs concurrently with the
core and increases the core’s bandwidth left for other system tasks. The system can take
advantage of this increased core bandwidth by lowering the system clock frequency and
voltage, which decreases the amount of power that is consumed.
16.3.1 Features
The following list summarizes the features of MPC823e DSP:
• 16 × 16-bit multiply and accumulate
• Load/store with automatic post increment/decrement
• DSP routine library provides 11 basic building blocks for implementation of V.34bis
and 56K
16.3.2 DSP Operation
There are three layers to DSP functionality—hardware, firmware, and software. You only
need to construct the software layer to generate an application.
Figure 16-7. DSP Functionality Implementation
CPM HARDWARE
CPM FIRMWARE
CPU SOFTWARE
GENERIC DSP MICROCODE ROUTINE LIBRARY
MAC AND ADDRESS GENERATOR MODULES
FUNCTION DESCRIPTOR CHAIN IN EXTERNAL
STORED IN THE INTERNAL ROM
IN CPM RISC MICROCONTROLLER ARCHITECTURE
MEMORY DEFINES THE SEQUENCE AND DATA
FLOW OF THE DSP FUNCTIONS
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