Introduction
MOTOROLA
MPC823e REFERENCE MANUAL
1-5
INTRODUCTION
1
❏
LCD Controller
— 1-, 2-, or 4-Bit Per Pixel Grayscale Mode Using Advanced Frame Rate Control
(FRC) Algorithm
— 4-, 8-, 9-, or 12-Bit Parallel Output to LCD Displays
— Programmable Display Active Area
— Nonsplit- or Vertically Split-Screen Support
— Uses Burst Read DMA Cycles for Maximum Bus Performance
— End-of-Frame Interrupt Generation
— Data for Splits—2+2 or 4+4 Parallel Bits (x+x Refers to x Bits Each for Lower
and Upper Screens in Parallel)
— Built-In Color RAM with 256 12-Bit Entries
— Programmable Wait Time Between Lines and Frames
— Panel Voltage Control Adjustments for Contrast Set with On-Chip Timers
— Programmable Polarity for All LCD Interface Signals
— Uses Burst Read DMA Cycles for Maximum Bus Performance
— End-of-Frame Interrupt Generation
• Single-Socket PCMCIA-ATA Interface
❏
Master Interface, Release 2.1-Compliant
❏
Single PCMCIA Socket
❏
Eight Memory or I/O Windows Available
❏
Eight General-Purpose I/O Pins and Two General-Purpose Output-Only Pins are
Available when the PCMCIA Controller is not in Operation
• Low-Power Support Modes
❏
Normal High–All Units are Fully Powered at High Clock Frequency
❏
Normal Low–All Units are Fully Powered at Low Clock Frequency
❏
Doze–Core Functional Units are Disabled, Except Timebase, Decrementer, PLL,
Memory Controller, Real-Time Clock, LCD, and Communication Processor Module
❏
Sleep–All Units Are Disabled, except Real-Time Clock, Periodic Interrupt Timer,
Timebase, and Decrementer. PLL Is Active for Fast Wake-up
❏
Deep Sleep–All Units are Disabled Including PLL, but not the Real-Time Clock and
Periodic Interrupt Timer, Timebase, and Decrementer
❏
Power-Down—All Units are Disabled Including PLL, but not the Real-Time Clock
and Periodic Interrupt Timer, Timebase, and Decrementer. Saves More Power than
Other Modes. The State of Certain Registers may be Preserved.
❏
Can be Dynamically Shifted Between High and Low Frequency Operation
To Next Page
