Communication Processor Module
MOTOROLA
MPC823e REFERENCE MANUAL
16-123
SERIAL
I/F
COMMUNICATION
16
PROCESSOR MODULE
The SWTR option gives station B the opportunity to listen to transmissions from station A
and transmit data to station A. To do this, station B would set the SWTR bit in its receive
route RAM. For this entry, receive data is taken from the L1TXDx pin and data is transmitted
on the L1RXDx pin. If you only want to listen to station A transmissions and not transmit data
on L1RXDx, then you must clear the CSEL field in the corresponding transmit route RAM
entry to prevent transmission on the L1RXDx pin.
It is also possible for station B to transmit data to station A by setting the SWTR bit of the
entry in its receive route RAM. Data is transmitted on the L1RXDx pin rather than the
L1TXDx pin, according to the transmit route RAM. This configuration could, however, cause
collisions with other data on the L1RXDx pin unless care is taken to choose an available
(quiet) time-slot. If you only want to transmit on L1RXDx and not receive data on L1TXDx,
then you must clear the CSEL field in the receive route RAM to prevent reception of data on
L1TXDx.
0 = Normal operation of the L1TXDx and L1RXDx pins.
1 = Data is transmitted on the L1RXDx pin and is received from the L1TXDx pin for the
duration of this entry.
SSEL1–SSEL4—Strobe Select 1–4
The four strobes—L1ST1, L1ST2, L1ST3, and L1ST4—can be assigned to the receive RAM
and asserted or negated with L1RCLKx. L1ST5, L1ST6, L1ST7, and L1ST8 can be
assigned to the transmit RAM and asserted or negated with L1TCLKx. Each bit corresponds
to the value the strobe must have during this bit/byte group. Multiple strobes can be asserted
simultaneously, if preferred. If a strobe is configured to be asserted in two consecutive serial
interface RAM entries, then it remains continuously asserted while the serial interface RAM
entries are being processed. If a strobe is asserted on the last entry in the table, the strobe
is negated after the last entry finishes processing.
Bit 6—Reserved
This bit is reserved and must be set to 0.
Note:
If the transmit and receive sections of the TDM do not use a single clock source,
the SWTR feature can cause erratic results to occur.
Note:
Each strobe is changed with the corresponding RAM clock and is only output if
the corresponding parallel I/O is configured as a dedicated pin.
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