Motorola MPC823e - Page 593

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-139
SERIAL
I/F
COMMUNICATION
16
PROCESSOR MODULE
16.7.5.4 SERIAL INTERFACE COMMAND REGISTER. The 8-bit serial interface
command register (SICMR) allows you to dynamically program the serial interface RAM.
The contents of this register are only valid in the RAM division mode. For more information
about dynamic programming, refer to Section 16.7.4.6 Serial Interface RAM Dynamic
Changes.
CSRRx—Change Shadow RAM for TDMA or B Receiver
When set, this bit causes the serial interface receiver to replace the current route with the
shadow RAM. You set this bit and the serial interface clears it.
0 = The receiver shadow RAM is not valid. You can write into the shadow RAM to
program a new routing.
1 = The receiver shadow RAM is valid. The serial interface exchanges between the
RAMs and take the new receive routing from the receiver shadow RAM. This bit is
cleared as soon as the switch has completed.
CSRTx—Change Shadow RAM for TDMA or B Transmitter
When set, this bit causes the serial interface transmitter to replace the current route with the
shadow RAM. You set this bit and the serial interface clears it.
0 = The transmitter shadow RAM is not valid. You can write into the shadow RAM to
program a new routing.
1 = The transmitter shadow RAM is valid. The serial interface exchanges between the
RAMs and take the new transmitter routing from the receiver shadow RAM. This
bit is cleared as soon as the switch has completed.
Bits 2–7—Reserved
These bits are reserved and must be set to 0.
SICMR
BIT 0 1 2 3 4 5 6 7
FIELD CSRRA CSRTA CSRRB CSRTB RESERVED
RESET 0000 0
R/W R/W R/W R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0xAE7