Motorola MPC823e - Page 599

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-145
SERIAL
I/F
COMMUNICATION
16
PROCESSOR MODULE
16.7.6.1 IDL INTERFACE IMPLEMENTATION. The MPC823e can identify and support
each IDL channel or it can output strobe lines for interfacing with devices that do not support
the IDL bus. The IDL signals for each transmit and receive channel are as follows:
• L1RCLKx—IDL clock pin. Input to the MPC823e.
• L1RSYNCx—IDL sync pin. Input to the MPC823e. This signal indicates that the clock
periods following the pulse designate the IDL frame.
• L1RXDx—IDL receive data pin. Input to the MPC823e. Valid only for the bits that are
supported by the IDL and ignored for other signals that may be present.
• L1TXDx—IDL transmit data pin. Output from the MPC823e. Valid only for the bits that
are supported by the IDL. Otherwise, it is three-stated.
• L1RQx—IDL request permission to transmit on the D channel. Output from the
MPC823e on the L1RQx pin.
• L1GRA—IDL grant permission to transmit on the D channel. Input to the MPC823e on
the L1TSYNCA pin.
The basic rate IDL bus has three channels:
• B1 is a 64kbps bearer channel
• B2 is a 64kbps bearer channel
• D is a 16kbps signaling channel