Motorola MPC823e - Page 620

Communication Processor Module
16-166 MPC823e REFERENCE MANUAL MOTOROLA
SCCs
COMMUNICATION
16
PROCESSOR MODULE
16.9.2 The General SCCx Mode Registers
The serial communication controllers contain two high and low read/write general SCCx
mode registers (GSMR_H and GSMR_L) that define all the options common to each serial
communication controller, regardless of the protocol. These registers are cleared at reset
and since they are 64 bits in length, they are accessed as GSMR_L and GSMR_H. GSMR_L
contains the first (low-order) 32 bits of the GSMR and GSMR_H contains the last 32 bits.
Bits 0–14—Reserved
These bits are reserved and must be set to 0.
GDE—Glitch Detect Enable
This bit determines whether a serial communication controller will search for glitches on the
external receive and transmit serial clock lines provided. If this feature is enabled, the
presence of a glitch is reported in the SCCE register for each particular protocol. Whether
or not the GDE bit is set, a serial communication controllers always attempts to clean up the
clocks that it uses internally, via a Schmitt trigger on the input lines.
0 = No glitch detection is performed. This option must be chosen if the external serial
clock exceeds the limits of the glitch detection logic (6.25MHz assuming a 25MHz
system clock). This option must also be chosen if the SCCx clock is provided by
one of the internal baud rate generators. Lastly, this option must be chosen if
external clocks are used and if it is more important to minimize power consumption
than to watch for glitches.
1 = Glitch detection is performed with a maskable interrupt generated in the SCCE
register.
GSMR_H
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
RESERVED GDE
RESET
0 0
R/W
R/W R/W
ADDR
(IMMR & 0xFFF0000) + 0xA24
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
TCRC REVD TRX TTX CDP CTSP CDS CTSS TFL RFW TXSY SYNL RTSM RSYN
RESET
0 0000000000 0 00
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFF0000) + 0xA26