Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-251
COMMUNICATION
16
SCCs
Figure 16-81. HDLC Interrupt Event Example
LINE IDLE
STORED IN RX BUFFER
FRAME
RECEIVED IN HDLC
TIME
RXDx
CDx
LINE IDLE
LINE IDLE
STORED IN
TX BUFFER
CTSx
LINE IDLE
TXDx
RTSx
IDL
CDx
CDxRXB
CTSx CTSxTXB
NOTES:
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CDx event must be programmed in the port C parallel I/O, not in the SCC itself.
6. F is set to flag, A is set to address byte, C is set to control byte, I is set to information byte, and CR is set to CRC byte.
NOTES:
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CTSx event must be programmed in the port C parallel I/O, not in the SCC itself.
HDLC SCCE
EVENTS
HDLC SCCE
EVENTS
FRAME
TRANSMITTED BY HDLC
F
A
A
C
I
CR CR
I
IF
RXF
FLG
IDL
F A A C CR CR FF
FLG FLG
F
FLG
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