Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-255
COMMUNICATION
16
SCCs
16.9.16.14 SCC2 HDLC PROGRAMMING EXAMPLE #1.The following initialization
sequence is for an SCC2 HDLC channel with an external clock. The SCC2 in HDLC mode
is configured with the RTS2
, CTS2, and CD2 pins active and the CLK3 pin is used for both
the HDLC receiver and transmitter.
1. Configure the port A pins to enable the TXD2 and RXD2 pins. Write PAPAR bits 13
and 12 with ones and then write PADIR and PAODR bits 13 and 12 with zeros.
2. Configure the port C pins to enable RTS2
, CTS2, and CD2. Write PCPAR bit 14 with
one, and bits 9 and 8 with zeros, PCDIR bits 14, 9, and 8 with zeros, and PCSO bits
9 and 8 with ones.
3. Configure port A to enable the CLK3 pin. Write PAPAR bit 5 with a one and PADIR bit
5 with a zero.
4. Connect the CLK3 pin to SCC2 using the serial interface. In the SICR, set the R2CS
and T2CS bits to 110.
5. Connect the SCC2 to the NMSI (its own set of pins) and clear the SC2 bit in the SICR.
6. Write 0x0001 to the SDCR to set the SDMA bus arbitration level to 5.
7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RX buffer
descriptor and TX buffer descriptors in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of dual-port RAM and one TX buffer descriptor following it,
write 0x2000 to RBASE and 0x2008 to TBASE.
8. Program the CPCR to execute the INIT RX AND TX PARAMS command for the
SCC2. This command causes the RBPTR and TBPTR parameters of the serial
channel to be updated with the new values just programmed into RBASE and TBASE.
9. Write 0x18 to the RFCR and 0x18 to the TFCR for normal operation.
10.Write h the maximum number of bytes per receive buffer to the MRBLR. Assume 256
bytes, so MRBLR = 0x0100. The value 256 is chosen so that an entire receive frame
can fit into one receive buffer.
11.Write 0x0000F0B8 to C_MASK to comply with 16-bit CCITT-CRC.
12.Write 0x0000FFFF to C_PRES to comply with 16-bit CCITT-CRC.
13.Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.
14.Write 0x0100 to MFLR so the maximum frame size is 256 bytes.
15.Write 0x0001 to RFTHR to allow interrupts after each frame.
16.Write 0x0000 to HMASK to allow all addresses to be recognized.
17.Clear HADDR1, HADDR2, HADDR3, and HADDR4 for clarity.
18.Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main
memory. Write 0xB000 to RX_BD_Status, write 0x0000 to RX_BD_Length (not
required), and 0x00001000 to RX_BD_Pointer.
19.Initialize the TX buffer descriptor. Assume the TX data frame is at 0x00002000 in main
memory and contains five 8-bit characters. Write 0xBC00 to TX_BD_Status, 0x0005
to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
20.Write 0xFFFF to the SCCE–HDLC to clear any previous events.
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