Communication Processor Module
MOTOROLA
MPC823e REFERENCE MANUAL
16-295
COMMUNICATION
16
SCCs
DCR—IrDA DPLL Clock Ratio
This field determines the clock ratio between the IrDA DPLL clock and the bit rate clock. This
field is valid only in high-speed mode.
00 = 12x bit rate clock.
01 = Reserved.
1x = Reserved.
FD—Full Duplex
0 = Data reception is disabled during the transmission process.
1 = Transmission and reception of data in parallel are enabled.
LOOP—Loop Mode
When set, this bit selects the local loopback operation. The transmitter output is internally
connected to the receiver input. The receiver and transmitter operate normally, except the
received data is ignored.
0 = Normal operation.
1 = The IrDA is in loopback mode.
MOD—Infrared Mode
Mode of operation.
00 = Low-speed mode (up to and including 115.2kb/s).
01 = Middle-speed (0.576Mb/s or 1.152Mb/s).
10 = High-speed (4.0Mb/s).
11 = Reserved.
EN—Enable IrDA
This bit enables IrDA decoder/encoder operation.
0 = IrDA is disabled.
1 = IrDA is enabled.
Note: The FD bit must be set in loopback mode.
Note: Changing the EN bit value is allowed only when the SCC2 is off (after the ENR
and ENT bits in the GSMR_L are cleared).
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