Motorola MPC823e - Page 750

Communication Processor Module
16-296 MPC823e REFERENCE MANUAL MOTOROLA
COMMUNICATION
16
PROCESSOR MODULE
SCCs
16.9.20.5.2 SCC2 Infrared Serial Interaction Pulse Control Register. The SCC2
infrared serial interaction pulse control (IRSIP) register controls the initiation of the serial
infrared interaction pulse.
Bits 0 and 3—Reserved
These bits are reserved and must be set to 0.
GS—Generate Serial Infrared Interaction Pulse
0 = Writing zero to this bit has no effect.
1 = Setting this bit generates a serial infrared interaction pulse, which occurs only
when the channel is idle. This bit is immediately reset by the IrDA controller.
TS—Timer Set
0 = The Timer 2 status has no effect on the serial infrared interaction pulse.
1 = The expiration of Timer 2 triggers the generation of a serial infrared interaction
pulse.
SHL—Serial Infrared Interaction Pulse High-Level Length
Program this field with the width of the SIP assertion part (in bit rate clock units).
SLL—Serial Infrared Interaction Pulse Low-Level Length
Program this field with the width of the SIP negation part (in bit rate clock units).
IRSIP
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD RES GS TS RES SHL SLL
RESET 0000 0 0
R/W R/W R/W R/W R/W R/W R/W
ADDR (IMMR & 0xFFF0000) + 0xA3A
Note: Reading the GS bit always returns a zero.