Motorola MPC823e - Page 751

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-297
COMMUNICATION
16
PROCESSOR MODULE
SCCs
16.9.20.5.3 Low-Speed IrDA Programming Guide. Low-speed infrared programming is
very similar to SCC2 ASYNC HDLC programming. The only difference is the value of EOF
and BOF in the SCC2 parameter RAM and the programming of the IRMODE register. Use
the following initialization sequence for low-speed infrared.
1. Initialize the SDCR with the appropriate arbitration ID.
2. Configure the port A and port C pins to enable RXD2 and TXD2. This assumes you
are using NMSI mode. If not, appropriately configure the time-slot assigner and pins.
3. Configure a baud rate generator to generate the appropriate channel clocking
frequency.
4. Program the SICR to route the baud rate generator clocking to an SCC2 in
asynchronous HDLC mode.
5. Select whether the channel is using the time-slot assigner or the NMSI pins in the
SICR.
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the first RX and TX
buffer descriptors.
7. Issue the INIT RX AND TX PARAMS command to SCC2.
8. Program RFCR and TFCR.
9. Write MRBLR with the maximum receive buffer size.
10.Write C_MASK and C_PRES with the standard values.
11.Write 0xC0 to BOF, 0xC1 to EOF and 0x7D to ESC.
12.Write 0 to the ZERO register in the SCC2 parameter RAM.
13.Program the RFTHR to the number of frames that must be received before an interrupt
is generated.
14.Program the transmit and receive control character tables.
15.Initialize all RX buffer descriptors.
16.Initialize all TX buffer descriptors.
17.Clear the SCCE–ASYNC HDLC register by writing 0xFFFF to it.
18.Program the SCCM–ASYNC HDLC register with the proper mask to allow all desired
interrupts.
19.Program the GSMR_H.
20.Program the MODE field of the GSMR_L to SCCx ASYNC HDLC mode, but do not
turn on the transmitter or receiver.
21.Write 0x0001 to the IRMODE register to enable low-speed infra-red.
22.Set the PSMR–SCC ASYNC HDLC register appropriately.
23.Turn on the transmitter and receiver in the GSMR_L by setting the ENT and ENR bits.