Motorola MPC823e

Communication Processor Module
16-304 MPC823e REFERENCE MANUAL MOTOROLA
COMMUNICATION
16
PROCESSOR MODULE
SCCs
16.9.21.4.1 Inline Synchronization Pattern. The transparent channel can be
programmed to transmit and receive a synchronization pattern if the SYNL field in the
GSMR_H are not zero. This pattern is defined in the data synchronization register and the
length of the Sync pattern is defined in the SYNL field. If the SYNL field is 00, then the DSR
is not used and an external Sync signal is used instead. See Section 16.9.4 Data
Synchronization Register and Section 16.9.2 The General SCCx Mode Registers for
more information.
DSR–SCC TRANSPARENT (SYNL = 01)
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD 4-BIT SYNC X
RESET 0111111001111110
R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0xA2E
NOTE: X = “Don’t Care”.
DSR–SCC TRANSPARENT (SYNL = 10)
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD 8-BIT SYNC X
RESET 0111111001111110
R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0xA2E
NOTE: X = “Don’t Care”.
DSR–SCC TRANSPARENT (SYNL = 11)
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD 16-BIT SYNC
RESET 0111111001111110
R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0xA2E