Communication Processor Module
16-456
MPC823e REFERENCE MANUAL
MOTOROLA
I
2
C
COMMUNICATION
16
PROCESSOR MODULE
16.13 THE I
2
C CONTROLLER
The inter-integrated circuits (I
2
C
®
) controller enables the MPC823e to exchange data with a
number of other I
2
C devices, such as microcontrollers, EEPROMs, real-time clock devices,
A/D converters, and LCD displays. The I
2
C controller is a synchronous, multimaster bus that
is used to connect several integrated circuits on a board. It uses two wires—serial data
(SDA) and serial clock (SCL)—to carry information between the integrated circuits that are
connected to it.
The I
2
C controller consists of transmitter and receiver sections, an independent baud rate
generator, and a control unit. The transmitter and receiver sections use the same clock, that
is derived from the I
2
C baud rate generator in master mode and generated externally in
slave mode. According to the I
2
C specification, wait states are inserted during a data transfer
if the SCL signal is held low by a slave device. As a master in the middle of a data transfer,
the I
2
C controller recognizes wait states by monitoring the SCL signal. The I
2
C controller
does not begin counting down from a specific timeout value when SCL is asserted, so the
software must monitor SCL assertion times for bus timeout.
The I
2
C receiver and transmitter are double-buffered, which corresponds to an effective
FIFO size of 2 characters. The MPC823e I
2
C bit 0 (MSB) is shifted out first. When the I
2
C is
not enabled in the I2MOD register, it consumes very little power.
Figure 16-126. I
2
C Controller Block Diagram
SHIFT REGISTER
TX DATA REGISTER
SHIFT REGISTER
RX DATA REGISTER MODE REGISTER
BRG
CONTROL
PERIPHERAL BUS
U-BUS
SDA
SCL
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