Communication Processor Module
MOTOROLA
MPC823e REFERENCE MANUAL
16-457
I
2
C
COMMUNICATION
16
PROCESSOR MODULE
16.13.1 Features
The following is a list of the I
2
C controller’s main features:
• Two-Pin Interface
• Full-Duplex Operation
• Master or Slave I
2
C Mode Support
• MultiMaster Environment Support
• Continuous Transfer Mode for Autoscanning Peripherals
• Supports Maximum Capacitive Load of 400
P
F on Both Bus Lines (Fully I
2
C-Compliant)
• Independent Programmable Baud Rate Generator
• Supports I
2
C Low- and High-Speed Operation
• Supports 7-Bit I
2
C Addressing
• Open-Drain Output Pins Support MultiMaster Configuration
• Local Loopback Capability for Testing
16.13.2 I
2
C Controller Clocking and Pin Functions
Both serial data (SDA) and serial clock (SCL) are bidirectional pins that must be connected
to a positive 5V power supply via an external pull-up resistor in the 6.8K Ohm to 10K Ohm
range. Both pins are high when the I
2
C bus is free. The SCL signal clocks in received data
and clocks out transmitted data on the SDA pin.
The I
2
C controller can be configured as a master or slave. When configured as a master, the
I
2
C controller generates SCL, and then initiates and terminates the I/O operation. In addition,
the I
2
C controller generates the SCL signal via a dedicated baud rate generator that takes
its input from BRGCLK, which is described in
Section 5.3.4.2 The Baud Rate Generator
Clock
. When configured as a slave, the I
2
C controller receives SCL as an input.
An I
2
C transaction is initiated when the master generates a start condition, which is defined
as the SDA signal making a high-to-low transition while SCL is high. An acknowledge (ACK)
is generated by the I
2
C receiver after each byte transfer. The receiver signals an ACK by
driving the SDA signal low during the SCL clock pulse immediately following each data byte
transmission. The data and ACK signals are always sampled on the rising edge of SCL. If
the receiver does not issue an ACK after a data byte is transmitted, the I
2
C master generates
a stop condition and transmission stops. A stop condition is when the SDA signal makes a
low to high transition while the SCL signal remains high, as illustrated in Figure 16-127.
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