Communication Processor Module
16-458
MPC823e REFERENCE MANUAL
MOTOROLA
I
2
C
COMMUNICATION
16
PROCESSOR MODULE
16.13.3 I
2
C Controller Transmission and Reception Process
16.13.3.1 I
2
C MASTER MODE.
When the I
2
C controller is in master mode, it initiates a
transaction by transmitting a message specifying a read or write operation to the I
2
C slave.
If a read operation is specified, the direction of the transfer is changed after the read
operation is acknowledged, and the slave device then becomes the transmitter. If a write
operation is specified, the direction of the transfer remains unchanged.
As the I
2
C controller shifts out each bit, it monitors the level of the SDA pin to detect a
possible collision with other I
2
C master transmitters. If a collision is detected, transmission
stops and the controller reverts to slave mode. A maskable interrupt may be issued to the
core to allow the software to retransmit later.
In master mode operation, setting the S bit in the TX buffer descriptor will cause a start
condition to be sent before this buffer is transmitted. If the TX buffer descriptor is the first
one in the ring, then a start condition will be issued, regardless of the S bit setting. Setting
the L bit will cause a stop condition to be sent after the buffer is transmitted. You must set
the L bit for the last TX buffer in the ring.
You must set the M/S bit in the I2COM register to configure the controller as a master. Clear
the I2CMOD register’s EN bit to disable the I
2
C controller before programming the SCL clock
frequency for the I2MOD and I2BRG registers. The I2ADD register does not need to be
programmed when you are operating the I
2
C controller in single-master mode. Enable the
I
2
C controller by setting the EN bit in the I2MOD register.
Figure 16-127. I
2
C Timing
SCL
SDA
DATA BYTE
START CONDITION
STOP CONDITION
A
C
K
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