Motorola MPC823e - Page 923

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-469
I
2
C
COMMUNICATION
16
PROCESSOR MODULE
EN—Enable I
2
C
This bit enables I
2
C operation. When EN is cleared, the I
2
C controller is in a reset state and
consumes minimal power.
0 = I
2
C controller is disabled.
1 = I
2
C controller is enabled.
16.13.7.2 I
2
C RECEIVE BUFFER DESCRIPTOR. Using receive (RX) buffer descriptors,
the communication processor module reports information about each buffer of received
data, closes the current buffer, generates a maskable interrupt, and starts receiving data in
the next buffer when the current buffer is full. In addition, it closes the buffer when a stop or
start condition is found on the I
2
C bus or when an overrun error occurs.
The first word of the RX buffer descriptor contains status and control bits, which you prepare
before reception and then the communication processor module sets them after the buffer
is closed. The second word contains the data length (in bytes) that is received and the third
and fourth words contain a pointer that always points to the beginning of the received data
buffer. The core writes these RX buffer descriptor bits before the I
2
C controller is enabled.
Note: Do not modify other bits of the I2MOD register when the EN bit is set or else
erratic operation will occur.
Note: The communication processor module sets all the status bits in this buffer
descriptor, but you must clear them before submitting the buffer descriptor to the
communication processor module.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OFFSET + 0
E RES WI L RESERVED OV RES
OFFSET + 2
DATA LENGTH
OFFSET + 4
RX DATA BUFFER POINTER
OFFSET + 6
NOTE: You are only responsible for initializing the items in bold.