Motorola MPC823e

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-508
CPIC
COMMUNICATION
16
PROCESSOR MODULE
IEN—Interrupt Enable
This bit is a master enable for the CPM interrupts.
0 = CPM interrupts are disabled.
1 = CPM interrupts are enabled.
SPS—Spread Priority Scheme
This bit selects the relative USB and SCCx priority scheme and cannot be changed
dynamically.
0 = Grouped. The USB and SCCs are grouped by priority at the top of the table.
1 = Spread. The USB and SCCs are spread by priority in the table.
16.15.5.2 CPM INTERRUPT PENDING REGISTER. Each bit in the 32-bit read/write CPM
interrupt pending register (CIPR) indicates which CPM interrupt sources require interrupt
service. When a CPM interrupt is received, the CPM interrupt controller sets the
corresponding bit in the CIPR.
In a vectored interrupt scheme, the CPM interrupt controller clears the bit in the CIPR that
corresponds to the current interrupt when the core acknowledges the interrupt. The core
acknowledges the interrupt by setting the IACK bit in the CIVR. The vector number that
corresponds to the CPM interrupt source is then available to the core in the CIVR. However,
the CIPR bit is not cleared if an event register exists for that interrupt source. Event registers
only exist for interrupt sources that have multiple source events. For example, the serial
communication controllers have multiple events that cause SCCx interrupts.
CIPR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
PC15 USB SCC2 SCC3 RES PC14
TIMER
1
PC13 PC12 SDMA IDMA1 IDMA2 RES
TIMER
2
R–TT I2C
RESET
0000000000000000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x944
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
PC11 PC10 RES
TIMER
3
PC9 PC8 PC7 RES
TIMER
4
PC6 SPI SMC1 SMC2 PC5 PC4 RES
RESET
0000000000000000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x946