Motorola MPC823e - Page 977

PCMCIA Interface
MOTOROLA MPC823e REFERENCE MANUAL 17-11
PCMCIA INTERFACE
17
If Card B and its socket are configured for I/O interface operation or if the card’s power
supply circuitry is using the IRQ signal, CBRDY is:
0 = Card B is requesting an interrupt.
1 = Card B is not requesting an interrupt.
Bits 24–31—Reserved
These bits are reserved and must be set to 0.
17.5.2 PCMCIA Interface Status Change Register
The PCMCIA interface status change register (PSCR) records changes in the state of the
PCMCIA input port signals. This register is reset by writing ones to it (writing zero has no
effect). However, bits 24 and 25 are level-triggered. To clear them, the external source of
the interrupt must be cleared.
Bits 0–15—Reserved
These bits are reserved and must be set to 0
CBVS1_C—Card B Voltage Sense 1 Change
0 = Signal is changed.
1 = Signal is unchanged.
CBVS2_C—Card B Voltage Sense 2 Change
0 = Signal is changed.
1 = Signal is unchanged.
PSCR
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
RESERVED
RESET
—
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xE8
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
CBVS1
_C
CBVS2
_C
CBWP_
C
CBCD2
_C
CBCD1
_C
CBBVD
2_C
CBBVD
1_C
RES
CBRDY
_L
CBRDY
_H
CBRDY
_R
CBRDY
_F
RESERVED
RESET
—
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xE8
NOTE: — = Undefined.