Panasonic MN101L Series

<Record of Changes - 2>
Details of revision from Ver.1.3 to Ver.1.4 in MN101LR05D/04D/03D/02D LSI User's Manual is shown below.
According to the details of revision, "Definition" of the table below is classified into seven groups.
Revision concerning descriptions in LSI User's Manual:
Writing error correction / Description change / Description addition / Description deletion
Revision concerning LSI specifications:
Specification change / Specification addition / Specification deletion
Modification (Ver.1.4)
Definition
Details of Revision
Page Title Line Ver.1.3 Ver.1.4
I-25 C. DC Char-
acteristics
C10 Specification addition - Supply current in HALT
I
DD10
MIN: - TYP: 0.2 µA MAX: 0.4 µA
C11
to
C14
Description change C10 I
DD10
to C13 I
DD13
C11 I
DD11
to C14 I
DD14
IV-12 Figure:4.1.2 - Writing error correction //Set the Clock mode Control Register
CLKMD.bit6-4 = 100
//Set the Clock mode Control Register
CLKMD.bit6-4 = 010
IV-30  Setting
Example of ...
- Writing error correction CPU outage in voltage transition: 16/
f
SCLK
(f
SCLK
= 32.768 kHz, 488 µs)
CPU outage in voltage transition: 32
/
f
SCLK
(f
SCLK
= 32.768 kHz, 977 µs)
VII-56 Table:7.11.5 - Writing error correction Setup Function
LCCTR0 LCDSEL
SEGSL0 COMSL4
1 1 COM4
1 0 SEG0
1 0 TM5IO(output)
1 0 TM5IO(input)
1 0 P73
Setup Function
LCCTR0 LCDSEL
SEGSL0 COMSL4
1 1 COM4
1 0 SEG0
0 - TM5IO(output)
0 - TM5IO(input)
0 - P73