Panasonic MN101L Series

<Record of Changes - 3>
Details of revision from Ver.1.2 to Ver.1.3 in MN101LR05D/04D/03D/02D LSI User's Manual is shown below.
According to the details of revision, "Definition" of the table below is classified into seven groups.
Revision concerning descriptions in LSI User's Manual:
Writing error correction / Description change / Description addition / Description deletion
Revision concerning LSI specifications:
Specification change / Specification addition / Specification deletion
Modification (Ver.1.3)
Definition
Details of Revision
Page Title Line Ver.1.2 Ver.1.3
I-10 Table:1.2.4 - Writing error correction Port: P46
Serial Interface: SBCS2A
Port: P46
Serial Interface: SBO1B/TXD1B
I-22 B. Operating
Condition
B15 Specification change Temperature/Voltage dependence
E
F5
MIN: -5.0 TYP: -- MAX: 5.0
Temperature/Voltage dependence
E
F5
MIN: -10.0 TYP: -- MAX: 10.0
B17 Specification change Temperature/Voltage dependence
E
F6
MIN: -15.0 TYP: -- MAX: 15.0
Temperature/Voltage dependence
E
F6
MIN: -20.0 TYP: -- MAX: 20.0
I-24 C. DC Char-
acteristics
C2 Specification change Operating supply current
I
DD2
MAX: 4.3 mA
Operating supply current
I
DD2
MAX: 3.0 mA
C3 Specification change Operating supply current
I
DD3
MAX: 3.4 mA
Operating supply current
I
DD3
MAX: 2.5 mA
C4 Specification change Operating supply current
I
DD4
MAX: 1.9 mA
Operating supply current
I
DD4
MAX: 1.5 mA
C6 Specification change Operating supply current
I
DD6
MAX: 0.45 mA
Operating supply current
I
DD6
MAX: 0.36 mA
I-25 C9 Specification change Supply current in HALT
I
DD9
MAX: 0.48 mA
Supply current in HALT
I
DD9
MAX: 0.33 mA
C12 Specification change Supply current in STOP
I
DD12
MAX: 0.12 µA
Supply current in STOP
I
DD12
MAX: 0.24 µA
I-37  Recom-
mended Con-
dition of Each
Pin
DMOD Description change ...the value of which is typically
between 100 Ω and 1000 Ω.
...the value of which is typically
between 1.5 kΩ and 100 kΩ. (Recom-
mendation: between 10 kΩ and 100
kΩ)
II-7 2.1.7 - Description change II-10 and 11 in 2.2 Memory Space Merged II-10 and 11 in ever 1.2 into
2.1.7 Address Space.
II-11 2.1.9 - Description change 2.2.1
Bank Function 2.1.9 Bank Function
II-13 2.1.10 - Description change 2.2.2 Special Function Register 2.1.10 Special Function Register
Table:2.1.5 - Specification change 0x03D8C: Reserved in Table: 2.2.2 0x03D8C: CLKMD
II-31 Note 2 - Writing error correction When recovering from Deep
STANDBY mode, ...
When recovering from SLOW/HALT2/
STOP0 mode, ...
IV-2 Table:4.1.1 - Description change 1. Internal high-speed oscillation...
...
4. External low-speed oscillation...
Table:4.1.1 Clock Oscillation Circuit
Figure:4.1.1 - Description change - Added operation enable control circuit.
IV-4 CPUM CLKSEL Writing error correction Select clock control
0: Low-speed clock (SCLK)
0: High-speed clock (HCLK)
Select clock control
0: Low-speed clock (SCLK)
1: High-speed clock (HCLK)
IV-4 Note 2 - Description addition - Set the PSW.MIE to "0" before chang-
ing the data of CPU or CKCTR...
Note 3 - Description addition - The instruction for changing the data of
CPUM or CKCTR must not be exe-
cuted in the internal RAM.