Philips LPC2101 - UART1 Interrupt Identification Register (U1 IIR - 0 Xe001 0008, Read Only)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 105
Philips Semiconductors
UM10161
Volume 1 Chapter 10: UART1
10.3.7 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read
Only)
The U1IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during
an U1IIR access, the interrupt is recorded for the next U1IIR access.
6:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
NA
7CTS
Interrupt
Enable
If auto-CTS mode is enabled this bit
enables/disables the modem status interrupt
generation on a CTS1 signal transition. If auto-CTS
mode is disabled a CTS1 transition will generate an
interrupt if Modem Status Interrupt Enable
(U1IER[3]) is set.
In normal operation a CTS1 signal transition will
generate a Modem Status Interrupt unless the
interrupt has been disabled by clearing the
U1IER[3] bit in the U1IER register. In auto-CTS
mode a transition on the CTS1 bit will trigger an
interrupt only if both the U1IER[3] and U1IER[7] bits
are set.
0
0 Disable the CTS interrupt.
1 Enable the CTS interrupt.
8 ABTOIntEn
0
U1IER8 enables the auto-baud time-out interrupt.
Disable Auto-baud Time-out Interrupt.
0
1 Enable Auto-baud Time-out Interrupt.
9 ABEOIntEn
0
U1IER9 enables the end of auto-baud interrupt.
Disable End of Auto-baud Interrupt.
0
1 Enable End of Auto-baud Interrupt.
31:10 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
NA
Table 105: UART1 Interrupt Enable Register (U1IER - address 0xE001 0004, when DLAB = 0)
bit description
Bit Symbol Value Description Reset value
Table 106: UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, read only)
bit description
Bit Symbol Value Description Reset value
0 Interrupt
Pending
0
Note that U1IIR[0] is active LOWLOW. The pending
interrupt can be determined by evaluating
U1IIR[3:1].
1
At least one interrupt is pending.
1 No interrupt is pending.