© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 181
Philips Semiconductors
UM10161
Volume 1 Chapter 14: A/D converter
14.4 Register description
The A/D Converter registers are shown in Tabl e 158.
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 158: ADC registers
Generic
Name
Description Access Reset
value
[1]
AD0
Address
& Name
ADCR A/D Control Register. The ADCR register must be
written to select the operating mode before A/D
conversion can occur.
R/W 0x0000 0001 0xE003 4000
AD0CR
ADGDR A/D Global Data Register. This register contains the
ADC’s DONE bit and the result of the most recent A/D
conversion.
R/W NA 0xE003 4004
AD0GDR
ADSTAT A/D Status Register. This register contains DONE and
OVERRUN flags for all of the A/D channels, as well as
the A/D interrupt flag.
RO 0x0000 0000 0xE003 4030
AD0STAT
ADINTEN A/D Interrupt Enable Register. This register contains
enable bits that allow the DONE flag of each A/D
channel to be included or excluded from contributing to
the generation of an A/D interrupt.
R/W 0x0000 0100 0xE003 400C
AD0INTEN
ADDR0 A/D Channel 0 Data Register. This register contains the
result of the most recent conversion completed on
channel 0.
RO NA 0xE003 4010
AD0DR0
ADDR1 A/D Channel 1 Data Register. This register contains the
result of the most recent conversion completed on
channel 1.
RO NA 0xE003 4014
AD0DR1
ADDR2 A/D Channel 2 Data Register. This register contains the
result of the most recent conversion completed on
channel 2.
RO NA 0xE003 4018
AD0DR2
ADDR3 A/D Channel 3 Data Register. This register contains the
result of the most recent conversion completed on
channel 3.
RO NA 0xE003 401C
AD0DR3
ADDR4 A/D Channel 4 Data Register. This register contains the
result of the most recent conversion completed on
channel 4.
RO NA 0xE003 4020
AD0DR4
ADDR5 A/D Channel 5 Data Register. This register contains the
result of the most recent conversion completed on
channel 5.
RO NA 0xE003 4024
AD0DR5
ADDR6 A/D Channel 6 Data Register. This register contains the
result of the most recent conversion completed on
channel 6.
RO NA 0xE003 4028
AD0DR6
ADDR7 A/D Channel 7 Data Register. This register contains the
result of the most recent conversion completed on
channel 7.
RO NA 0xE003 402C
AD0DR7
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