Philips LPC2101 - Power Control Usage Notes; Reset

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 33
Philips Semiconductors
UM10161
Volume 1 Chapter 3: System control block
3.9.4 Power control usage notes
After every reset, the PCONP register contains the value that enables all interfaces and
peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application has no need to
access the PCONP in order to start using any of the on-board peripherals.
Power saving oriented systems should have 1’s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
3.10 Reset
Reset has two sources on the LPC2101/02/03: the RESET pin and watchdog reset. The
RESET
pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip
Reset by any source starts the wake-up timer (see description in Section 3.12 “
Wake-up
Table 26: Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
Bit Symbol Description Reset
value
0 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
1 PCTIM0 Timer/Counter 0 power/clock control bit. 1
2 PCTIM1 Timer/Counter 1 power/clock control bit. 1
3 PCUART0 UART0 power/clock control bit. 1
4 PCUART1 UART1 power/clock control bit. 1
6:5 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
7PCI2C0The I
2
C0 interface power/clock control bit. 1
8 PCSPI The SPI interface power/clock control bit. 1
9 PCRTC The RTC power/clock control bit. 1
10 PCSPI The SSP interface power/clock control bit. 1
11 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
12 PCAD A/D converter 0 (ADC0) power/clock control bit.
Note: Clear the PDN bit in the ADCR before clearing this bit, and set
this bit before setting PDN.
1
18:13 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
19 PCI2C1 The I
2
C1 interface power/clock control bit. 1
27:20 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
28 PCTIM2 The Timer/Counter 2 power/clock control bit. 1
29 PCTIM3 The Timer/Counter3 power/clock control bit. 1
31:30 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA