© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 195
Philips Semiconductors
UM10161
Volume 1 Chapter 15: Timer0 and Timer1
[1] On Timer0, CAP0.3 is disabled and values for CAP3RE, CAP3FE, and CAP3I are not defined.
15.5.11 External Match Register (EMR, TIMER0: T0EMR - 0xE000 403C; and
TIMER1: T1EMR - 0xE000 803C)
The External Match Register provides both control and status of the external match pins
MAT(0-3).
If the match ouputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (Section 15.5.13 “
Rules for single edge
controlled PWM ouputs” on page 197).
10 CAP3FE 1 Capture on CAPn.3 falling edge: a sequence of 1 then 0 on CAPn.3 will cause CR3 to
be loaded with the contents of TC
[1]
.
0
0 This feature is disabled.
11 CAP3I 1 Interrupt on CAPn.3 event: a CR3 load due to a CAPn.3 event will generate an
interrupt
[1]
.
0
0 This feature is disabled.
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 170: Capture Control Register (CCR, TIMER0: T0CCR - address 0xE000 4028 and TIMER1: T1CCR - address
0xE000 8028) bit description
Bit Symbol Value Description Reset
value
Table 171: External Match Register (EMR, TIMER0: T0EMR - address 0xE000 403C and TIMER1: T1EMR -
address0xE000 803C) bit description
Bit Symbol Description Reset
value
0 EM0 External Match 0. This bit reflects the state of output MAT0.0/MAT1.0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the
functionality of this output.
0
1 EM1 External Match 1. This bit reflects the state of output MAT0.1/MAT1.1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the
functionality of this output.
0
2 EM2 External Match 2. This bit reflects the state of output MAT0.2/MAT1.2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output.
0
3 EM3 External Match 3. This bit reflects the state of output MAT0.3/MAT1.3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control
the functionality of this output.
0
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. Ta bl e 1 72
shows the encoding of these bits.
00
7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1. Ta bl e 1 72
shows the encoding of these bits.
00
To Next Page
Loading...