© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 215
Philips Semiconductors
UM10161
Volume 1 Chapter 17: RTC
17.4.1 RTC interrupts
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the
time counters. If CIIR is enabled for a particular counter, then every time the counter is
incremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm
compares. If all nonmasked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of power-down mode if the RTC is
operating from its own oscillator on the RTXC1-2 pins. When the RTC interrupt is enabled
for wake-up and its selected event occurs, X1/2 pins associated oscillator wake-up cycle is
started. For details on the RTC based wake-up process see Section 3.5.3 “
Interrupt
Wake-up register (INTWAKE - 0xE01F C144)” on page 20 and Section 3.12 “Wake-up
timer” on page 37.
17.4.2 Miscellaneous register group
Table 185 summarizes the registers located from 0 to 7 of A[6:2]. More detailed
descriptions follow.
17.4.3 Interrupt Location Register (ILR - 0xE002 4000)
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt (see Table 1 86
). Writing a one to the appropriate bit clears the
corresponding interrupt. Writing a zero has no effect. This allows the programmer to read
this register and write back the same value to clear only the interrupt that is detected by
the read.
Table 185: Miscellaneous registers
Name Size Description Access Address
ILR 2 Interrupt Location. Reading this location
indicates the source of an interrupt. Writing a
one to the appropriate bit at this location clears
the associated interrupt.
R/W 0xE002 4000
CTC 15 Clock Tick Counter. Value from the clock
divider.
RO 0xE002 4004
CCR 4 Clock Control Register. Controls the function of
the clock divider.
R/W 0xE002 4008
CIIR 8 Counter Increment Interrupt. Selects which
counters will generate an interrupt when they
are incremented.
R/W 0xE002 400C
AMR 8 Alarm Mask Register. Controls which of the
alarm registers are masked.
R/W 0xE002 4010
CTIME0 32 Consolidated Time Register 0 RO 0xE002 4014
CTIME1 32 Consolidated Time Register 1 RO 0xE002 4018
CTIME2 32 Consolidated Time Register 2 RO 0xE002 401C
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