Philips LPC2101 - PWM Control Register (PWMCON, TIMER0: PWM0 CON - 0 Xe000 4074 and TIMER1: PWM1 CON - 0 Xe000 8074)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 196
Philips Semiconductors
UM10161
Volume 1 Chapter 15: Timer0 and Timer1
15.5.12 PWM Control Register (PWMCON, TIMER0: PWM0CON - 0xE000 4074
and TIMER1: PWM1CON - 0xE000 8074)
The PWM Control Register is used to configure the match ouputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three single edge controlled PWM ouputs can be selected
on the MATn.2:0 outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM ouputs are cleared.
9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. Ta bl e 1 72
shows the encoding of these bits.
00
11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3. Ta bl e 172
shows the encoding of these bits.
00
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 171: External Match Register (EMR, TIMER0: T0EMR - address 0xE000 403C and TIMER1: T1EMR -
address0xE000 803C) bit description
Bit Symbol Description Reset
value
Table 172: External match control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Function
00 Do Nothing.
01 Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
10 Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
11 Toggle the corresponding External Match bit/output.
Table 173: PWM Control Register (PWMCON, TIMER0: PWM0CON - 0xE000 4074 and
TIMER1: PWM1CON - 0xE000 8074) bit description
Bit Symbol Description Reset value
0 PWM enable When one, PWM mode is enabled for MATn.0. When
zero, MATn.0 is controlled by EM0.
0
1 PWM enable When one, PWM mode is enabled for MATn.1. When
zero, MATn.1 is controlled by EM1.
0
1 PWM enable When one, PWM mode is enabled for MATn.2. When
zero, MATn.2 is controlled by EM2.
0
1 PWM enable When one, PWM mode is enabled for MATn.3. When
zero, MATn.3 is controlled by EM3.
Note: It is recommended to use MATn.3 to set the PWM
cycle because MATn.3 is not pinned out on Timer0.
0
4:32 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA