© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 42
Philips Semiconductors
UM10161
Volume 1 Chapter 4: MAM Module
[1] Instruction prefetch is enabled in modes 1 and 2.
[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
4.5 MAM configuration
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
4.6 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
4.7 MAM Control register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 3 3.
Following Reset, MAM functions are disabled. Changing the MAM operating mode causes
the MAM to invalidate all of the holding latches, resulting in new reads of Flash information
as required.
Table 31: MAM responses to data and DMA accesses of various types
Data Memory Request Type MAM Mode
0 1 2
Sequential access, data in latches Initiate Fetch
[1]
Initiate Fetch
[1]
Use Latched
Data
Sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch
Non-sequential access, data in latches Initiate Fetch
[1]
Initiate Fetch
[1]
Use Latched
Data
Non-sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch
Table 32: Summary of MAM registers
Name Description Access Reset
value
[1]
Address
MAMCR Memory Accelerator Module Control Register.
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See Tabl e 33 .
R/W 0x0 0xE01F C000
MAMTIM Memory Accelerator Module Timing control.
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
R/W 0x07 0xE01F C004
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