© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 188
Philips Semiconductors
UM10161
Volume 1 Chapter 15: Timer0 and Timer1
Two match registers can be used to provide a single edge controlled PWM output on the
MATn.2.0 pins. Because the MAT0.3 register is not pinned out on Timer0, it is
recommended to use the MRn.3 registers to control the PWM cycle length. One other
match register is needed to control the PWM edge position. The remaining two match
registers can be used to create PWM output with the PWM cycle rate determined by
MRn.3.
15.4 Pin description
Table 164 gives a brief summary of each of the Timer/Counter related pins.
15.5 Register description
Each Timer/Counter contains the registers shown in Tabl e 165. More detailed descriptions
follow.
Table 164: Timer/Counter pin description
Pin Type Description
CAP0.2.0
CAP1.3.0
Input Capture Signals- A transition on a capture pin can be configured to
load one of the Capture Registers with the value in the Timer Counter
and optionally generate an interrupt.
Here is the list of all CAPTURE signals, together with pins on where
they can be selected:
• CAP0.0: P0.2
• CAP0.1: P0.4
• CAP0.2: P0.6
• CAP1.0: P0.10
• CAP1.1: P0.11
• CAP1.2: P0.17
• CAP1.3: P0.18
Timer/Counter block can select a capture signal as a clock source
instead of the PCLK derived clock. For more details see Section 15.5.3
“Count Control Register (CTCR, TIMER0: T0CTCR - 0xE000 4070
and TIMER1: T1TCR - 0xE000 8070)” on page 191.
MAT0.2.0
MAT1.3.0
Output External Match Output 0/1- When a match register 0/1 (MR3:0) equals
the timer counter (TC), this output can either toggle, go LOW, go
HIGH, or do nothing. The External Match Register (EMR) and the
PWM Control register (PWMCON) control the functionality of this
output.
Here is the list of all MATCH signals together with pins on where they
can be selected:
• MAT0.0: P0.3
• MAT0.1: P0.5
• MAT0.2: P0.16
• MAT1.0: P0.12
• MAT1.1: P0.13
• MAT1.2: P0.19
• MAT1.3: P0.20
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