Philips LPC2101 - Capture Control Register (CCR, TIMER0: T0 CCR - 0 Xe000 4028 and TIMER1: T1 CCR - 0 Xe000 8028); Capture Registers (CR0 - CR3)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 194
Philips Semiconductors
UM10161
Volume 1 Chapter 15: Timer0 and Timer1
15.5.9 Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
15.5.10 Capture Control Register (CCR, TIMER0: T0CCR - 0xE000 4028 and
TIMER1: T1CCR - 0xE000 8028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Table 170: Capture Control Register (CCR, TIMER0: T0CCR - address 0xE000 4028 and TIMER1: T1CCR - address
0xE000 8028) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE 1 Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to
be loaded with the contents of TC.
0
0 This feature is disabled.
1 CAP0FE 1 Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to
be loaded with the contents of TC.
0
0 This feature is disabled.
2 CAP0I 1 Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt. 0
0 This feature is disabled.
3 CAP1RE 1 Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to
be loaded with the contents of TC.
0
0 This feature is disabled.
4 CAP1FE 1 Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to
be loaded with the contents of TC.
0
0 This feature is disabled.
5 CAP1I 1 Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt. 0
0 This feature is disabled.
6 CAP2RE 1 Capture on CAPn.2 rising edge: A sequence of 0 then 1 on CAPn.2 will cause CR2 to
be loaded with the contents of TC.
0
0 This feature is disabled.
7 CAP2FE 1 Capture on CAPn.2 falling edge: a sequence of 1 then 0 on CAPn.2 will cause CR2 to
be loaded with the contents of TC.
0
0 This feature is disabled.
8 CAP2I 1 Interrupt on CAPn.2 event: a CR2 load due to a CAPn.2 event will generate an interrupt. 0
0 This feature is disabled.
9 CAP3RE 1 Capture on CAPn.3 rising edge: A sequence of 0 then 1 on CAPn.3 will cause CR3 to
be loaded with the contents of TC
[1]
.
0
0 This feature is disabled.