© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 46
Philips Semiconductors
UM10161
Volume 1 Chapter 5: VIC
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
5.4 VIC registers
The following section describes the VIC registers in the order in which they are used in the
VIC logic, from those closest to the interrupt request inputs to those most abstracted for
use by software. For most people, this is also the best order to read about the registers
when learning the VIC.
5.4.1 Software Interrupt register (VICSoftInt - 0xFFFF F018)
The contents of this register are ORed with the 32 interrupt requests from the various
peripherals, before any other logic is applied.
VICVectAddr12 Vector address 12 register. R/W 0 0xFFFF F130
VICVectAddr13 Vector address 13 register. R/W 0 0xFFFF F134
VICVectAddr14 Vector address 14 register. R/W 0 0xFFFF F138
VICVectAddr15 Vector address 15 register. R/W 0 0xFFFF F13C
VICVectCntl0 Vector control 0 register. Vector Control Registers 0-15 each
control one of the 16 vectored IRQ slots. Slot 0 has the
highest priority and slot 15 the lowest.
R/W 0 0xFFFF F200
VICVectCntl1 Vector control 1 register. R/W 0 0xFFFF F204
VICVectCntl2 Vector control 2 register. R/W 0 0xFFFF F208
VICVectCntl3 Vector control 3 register. R/W 0 0xFFFF F20C
VICVectCntl4 Vector control 4 register. R/W 0 0xFFFF F210
VICVectCntl5 Vector control 5 register. R/W 0 0xFFFF F214
VICVectCntl6 Vector control 6 register. R/W 0 0xFFFF F218
VICVectCntl7 Vector control 7 register. R/W 0 0xFFFF F21C
VICVectCntl8 Vector control 8 register. R/W 0 0xFFFF F220
VICVectCntl9 Vector control 9 register. R/W 0 0xFFFF F224
VICVectCntl10 Vector control 10 register. R/W 0 0xFFFF F228
VICVectCntl11 Vector control 11 register. R/W 0 0xFFFF F22C
VICVectCntl12 Vector control 12 register. R/W 0 0xFFFF F230
VICVectCntl13 Vector control 13 register. R/W 0 0xFFFF F234
VICVectCntl14 Vector control 14 register. R/W 0 0xFFFF F238
VICVectCntl15 Vector control 15 register. R/W 0 0xFFFF F23C
Table 35: VIC register map
Name Description Access Reset
value
[1]
Address
Table 36: Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol ----TIMER3TIMER2--
Access R/W R/W R/W R/W R/W R/W R/W R/W
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