© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 208
Philips Semiconductors
UM10161
Volume 1 Chapter 16: Timer2 and Timer3
16.5.11 External Match Register (EMR, TIMER2: T2EMR - 0xE007 003C; and
TIMER3: T3EMR - 0xE007 403C)
The External Match Register provides both control and status of the external match pins
MAT(0-3).
If the match ouputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (Section 16.7 “
Rules for single edge controlled
PWM ouputs” on page 209).
Table 181: External Match Register (EMR, TIMER2: T2EMR - address 0xE007 003C and TIMER3: T3EMR -
address0xE007 4016-bit3C) bit description
Bit Symbol Description Reset
value
0 EM0 External Match 0. This bit reflects the state of output MAT2.0/MAT3.0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the
functionality of this output.
0
1 EM1 External Match 1. This bit reflects the state of output MAT2.1/MAT3.1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the
functionality of this output.
0
2 EM2 External Match 2. This bit reflects the state of output MAT2.2/MAT3.2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output.
0
3 EM3 External Match 3. This bit reflects the state of output MAT2.3/MAT3.3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control
the functionality of this output.
0
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. Ta bl e 1 82
shows the encoding of these bits.
00
7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1. Ta bl e 1 82
shows the encoding of these bits.
00
9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. Ta bl e 1 82
shows the encoding of these bits.
00
11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3. Ta bl e 182
shows the encoding of these bits.
00
15:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 182: External match control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Function
00 Do Nothing.
01 Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
10 Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
11 Toggle the corresponding External Match bit/output.
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