© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 50
Philips Semiconductors
UM10161
Volume 1 Chapter 5: VIC
5.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as IRQ. It does not differentiate between vectored and
non-vectored IRQs.
Bit 23 22 21 20 19 18 17 16
Symbol ----I2C1AD0-EINT2
Access R/W R/W R/W R/W R/W R/W R/W R/W
Bit 15 14 13 12 11 10 9 8
Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -
Access R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1 0
Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 47: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description
Bit Symbol Value Description Reset
value
31:0 See
VICIntSelect
bit allocation
table.
0 The interrupt request with this bit number is assigned to the IRQ
category.
0
1 The interrupt request with this bit number is assigned to the FIQ
category.
Table 48: IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol ----TIMER3TIMER2--
Access RO RO RO RO RO RO RO RO
Bit 23 22 21 20 19 18 17 16
Symbol ----I2C1AD0-EINT2
Access RO RO RO RO RO RO RO RO
Bit 15 14 13 12 11 10 9 8
Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -
Access RO RO RO RO RO RO RO RO
Bit 7 6 5 4 3 2 1 0
Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT
Access RO RO RO RO RO RO RO RO
Table 49: IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit description
Bit Symbol Description Reset
value
31:0 See
VICIRQStatus
bit allocation
table.
A bit read as 1 indicates a corresponding interrupt request being enabled,
classified as IRQ, and asserted
0
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